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Which limitation exists because of quantum tunneling in CMOS scaling?

A)Increased gate leakage current
B)Reduced channel mobility
C)Higher subthreshold swing
D)Lower breakdown voltage

💡 Explanation

Increased gate dielectric thinning causes a significant rise in undesirable gate leakage current, because electrons tunnel through potential energy barriers; therefore, leakage increases exponentially rather than decreasing with expected scaling, impacting performance.

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