Which mechanism limits current flow when shrinking CMOS transistor gate oxide thickness below 1nm?

💡 Explanation

When gate oxide thickness shrinks below 1nm, electron tunneling occurs because quantum mechanics allows electrons to pass through the potential barrier of the thin oxide, leading to leakage current increase. Therefore, electron tunneling limits current flow, rather than channel resistance, surface scattering, or reduced mobility, which dominate at larger dimensions or different bias conditions.

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