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Which processing bottleneck arises when time skew exceeds acceptable limits within a synchronous digital hierarchy (SDH) network?

A)Pointer justification errors increase
B)Clock drift causes bit errors
C)Jitter locks the PLL circuit
D)Framing errors cause data loss

💡 Explanation

Increased time skew causes pointer justification errors within SDH, because the buffer slips during frame alignment, leading to data corruption, therefore justification actions become excessively frequent, rather than maintaining smooth clock synchronization under normal skew conditions.

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